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Bukunmi Ayanlowo

Bukunmi Ayanlowo

FPGA Design Engineering Intern

Talent
RichmondMember since July 27, 2026
SystemVerilogVerilogVHDLModelSimVivadoQuartusDE1-SoCZynq Ultrascale+AssemblyC++MATLABPythonTcl
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SystemVerilogVerilogVHDLModelSimVivado

About

Ported and packaged video encoding and decoding IP cores from vendor reference designs into internal proprietary ecosystems using VHDL, optimizing for resource utilization. Architected custom digital systems on Zynq Ultrascale+ platforms through Xilinx Vivado, implementing AXI4 communication protocols to interface IP cores with memory and peripherals. Developed and tested C-based software applications referencing vendor designs to verify the functionality and reliability of the IP cores.

Experience

FPGA Design Engineering Intern - Evertz Microsystems

(2024-05 - 2025-08)

  • Ported and packaged video encoding and decoding IP cores from vendor reference designs into internal proprietary ecosystems using VHDL, optimizing for resource utilization.
  • Architected custom digital systems on Zynq Ultrascale+ platforms through Xilinx Vivado, implementing AXI4 communication protocols to interface IP cores with memory and peripherals.
  • Developed and tested C-based software applications referencing vendor designs to verify the functionality and reliability of the IP cores.
  • Conducted on-chip hardware verification and real-time debugging using Vivado Integrated Logic Analyzer (Chipscope), effectively isolating logic errors.

Electrical Team Member - Robotics for Space EXploration (RSX)

(2023-09 - 2024-01)

  • Collaborated in a multidisciplinary team to design and integrate the electrical subsystem for a Mars exploration rover.
  • Programmed and tested Arduino-based controllers to process sensor inputs and remote control systems.

Education

Bachelor of Applied Science - Electrical Engineering - University of Toronto

Skills

FPGA Design Engineering Intern

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