Jason Zhao

10+ years of FPGA development experience;

Strong RTL design skills using VHDL and Verilog;

skilled in use of EDA tools, such as VCS, Modelsim, Vivado, etc

Familiarity with SoC interconnects (AXI), high-speed protocols (PCIe, Ethernet), low-speed protocols(CAN, UART, SPI,1553B), and DDR3/4 controller