Zum Hauptinhalt springen
Milena Josipovic

Milena Josipovic

ASIC design verification engineer

Talente
BaselMitglied seit 8. Mai 2026
digital design verificationdebuggingUVMeRMSpecman eVerilogCadence MaestroPCIeEthernetI2CPSIFlexRayUARTGit
·

Diese Person einstellen

Senden Sie diesem Kandidaten direkt ein Jobangebot

digital design verificationdebuggingUVMeRMSpecman e

Über

Dedicated verification engineer with a strong drive for continuous learning. Offering over seven years of experience in semiconductor industry for automotive and high-performance computing applications. Experienced in constrained-random and metric-driven verification, as well as module and top-level digital and mixed-signal verification and analog modeling. Good knowledge of Cadence tools. Strong communicational skills, experienced in collaborating with global, cross-functional teams.

Berufserfahrung

Verification engineer at Openchip (2025-10 – Present)

  • Verification of PCIe gen 6 subystem
  • Third party IP integration - AXI, APB, PCIe
  • Register model scripts, register model integration
  • Study of HPC protocols - Ultra Ethernet, PCIe gen 6, UA link

Electronics and semicon engineer, grade B2 at Capgemini engineering (2023-11 – 2025-09)

  • writing test cases in System Verilog UVM
  • Regression setup and debugging
  • Coverage closure
  • Mentoring younger engineers

AMS engineer at HDL design house (acquired by Capgemini in November 2023) (2020-10 – 2023-10)

  • Writing and debugging AMS and DMS top level test cases, coding in System Verilog according to UVM
  • Verification environment maintenance
  • Writing Verilog AMS models for: differential output voltage charge pump, safety voltage regulator; writing functional and x-state tests in Cadence Maestro
  • Daily meetings with digital and analog designers and digital verification engineers to report status and align on top level testing
  • Managing team of 4 engineers – writing test plans and sharing tasks

Digital design verification engineer at Chipglobe GmbH (2019-02 – 2020-09)

  • Development of APB2UART verification environment (two UVCs and register model), System Verilog and UVM
  • Development of memory model using uvm mem as a parent class
  • Verification of protocols: SENT, PSI, PSI5, Flexray and I2C; Specman e according to eRM
  • Writing verification plans, maintenance of environments, coverage closure, FSDB generation for power analysis

Ausbildung

Master of Science in Electronics and digital systems – University of Belgrade, School of Electrical engineering (2026-09)

Bachelor of Science in Electrical engineering and computer science – University of Belgrade, School of Electrical engineering (2019-09)

Fähigkeiten

ASIC design verification engineer

Bewertungen

Verwandt