Design Engineer (武汉/上海)

该职位来源于猎聘 Responsibilities :

• Contribute to chip- and block-level architecture specification.
• Implement RTL in Verilog/System Verilog.
• Perform RTL and gate-level simulation/verification.
• Drive synthesis and timing closure. Collaborate with cross-functional teams to deliver tape-out. Qualifications:
• Bachelor’s degree or above in IC, microelectronics, optoelectronics, telecommunications, etc.
• Solid digital-design fundamentals, fluent in Verilog/System Verilog.
• Hands-on experience with EDA tools and full IC design flow.
• Proficient in Tcl/Shell/Perl/Python scripting.
• Fast learner, able to solve problems independently, strong team player. Excellent written and spoken English.