数字设计专家（高速retimer芯片）

该职位来源于猎聘 Key requirements: 硕士，10年数字研发，擅长高速retimer芯片，如PCIe或者Ethernet retimer芯片 Job Responsibilities.

• This position is for a Digital/ASIC Design Engineer to build next-generation Analog/Mixed-signal ASIC chipsets.
• Work closely with Analog/Mixed-signal designers to build robust system-on-chip that is reliable under PVT variation.
• Handle many aspects of ASIC design flow including: architecture, RTL coding/Verification, Synthesis, DFT, STA and P&R (for backend designer).
• Participate in chip debug, validation, and marketing specifications.
• Other tasks assigned by line manager. Qualifications:
• MSEE，10年数字研发，擅长高速retimer芯片，如PCIe或者Ethernet retimer芯片
• Excellent knowledge of ASIC design, such as arithmetic structure (addition, multiplication, integration), timing analysis, DFT, meta-stability, etc.
• Fundamental understanding of digital signal processing, such as FIR/IIR filter structure, error correction, and decimation.
• Desired usage experience of mainsteam industry-standard EDA tools, such as VCS/NC, Design Compiler, PrimeTime, Formality/ Conformal and Tetramax/DFT compiler.
• Experience in several vertical aspects of ASIC design (front-end and back-end) will be a great plus.
• Experience in common protocols, such as bus design (I2C, AHB/APB/AXI), datapath design (Filter, correlation or Cordic) and logic control (PCS or MAS) is a plus.
• Experience in metrics-driven verification methodology (System-Verilog/UVM based) is a plus.
• Experience in mixed-signal SOC design is a plus.
• Experience in perl/python/tcl scripts is a plus.