Ananya Ashok

Embedded Software Engineer mit Fokus auf C/C++ Entwicklung für performancekritische und echtzeitnahe Embedded-Systeme. Erfahrung in System-Performance-Analyse, Hardware-Software-Integration sowie Low-Level-Entwicklung auf Embedded-Plattformen (Linux, UIO, DMA, BRAM).

Fundierter

Hintergrund im Debugging und in der Validierung komplexer Systemverhalten über Hardware- und Software-Grenzen hinweg, einschließlich System-Boot und Integration. Vertraut mit Kommunikationsprotokollen wie Ethernet, CAN, SOME/IP, SPI und I2C. Fließend in Englisch, derzeit Verbesserung der Deutschkenntnisse (A2), mit starkem Interesse an sicherheitskritischen und satellitenbezogenen Embedded-Systemen.

Embedded Software Engineer at Akkodis (2024-02 – 2025-10)

Performed automated ECU validation, debugging, and system integration testing

• Performed automated ECU validation using ECU-Test (AmTS), executing structured test suites for system-level verification
• Analyzed ECU state transitions and timing behavior, identifying inconsistencies in system coordination
• Debugged sleep/wakeup issues across multiple ECUs, tracing wake-up triggers and eliminating software polling conditions blocking low-power states
• Investigated runtime and integration issues in distributed ECU architectures, including CAN, SOME/IP, Ethernet and SPI communication
• Conducted post-flash validation (smoke/sanity testing) and reported defects with structured root-cause analysis in Agile workflows
• Strengthened system stability through log analysis (DLT) and cross-component debugging

Werkstudent & Master Thesis at Akkodis (2023-04 – 2024-01)

Developed Embedded Linux drivers and real-time image processing pipeline on Xilinx Zynq-7000

• Developed Embedded Linux drivers (UIO, DMA, BRAM) on Xilinx Zynq-7000 (ARM + FPGA SoC)
• Implemented high-throughput data transfer between Processing System (PS) and Programmable Logic (PL) using AXI/CDMA
• Designed a real-time image processing pipeline in C++, enabling flexible execution on PS vs PL based on latency and throughput constraints
• Performed hardware-in-the-loop (HIL) style system validation, debugging interactions across FPGA and Linux layers
• Conducted performance benchmarking and latency analysis, optimizing data flow and system responsiveness
• Developed strong understanding of system architecture and module-level impact on overall system behavior

Intern at Bertrandt (2022-10 – 2023-03)

Developed C++ image processing algorithms and sensor fusion for autonomous vehicle prototypes

• Developed C++ (OpenCV-based) image processing algorithms for lane detection in autonomous vehicle prototypes
• Built and tested obstacle detection and avoidance functionality using camera + ToF (VL53L0X) sensor fusion
• Implemented sensor drivers (I2C) and processed raw sensor data, including calibration and noise handling
• Designed vehicle control logic (steering, lane switching) using ROS (C++), integrating perception with actuation
• Worked directly on real robotic hardware (Raspberry Pi, Jetson Nano), validating behavior under real conditions

Masters in Embedded systems and Microelectronics – Hochschule Darmstadt University of Applied Sciences (2021-09 – 2024-10)

Bachelor of Engineering in Telecommunications and Electronics – B.M.S Institute of Information & Technology (2015-06 – 2019-08)