Vasco Martins

I have extensive experience in physical layout engineering from transistor level, IP development to floor plan and costumer delivery tape out verifications.

I have worked in multiple high end products that are currently in the market providing high-yield success for the clients and foundries involved.

• Senior Layout Engineer with experience in all stages of Layout development from Floor Planning to Transistor level.
• Collaborated in the development of several high yield, large revenue silicon proven chips currently in the market for companies like Apple, Samsung, Huawei and Dell.
• Experienced in timeline estimations, project management, quality control and Tapeout verifications for GDSII customer/foundry delivery.
• Delivered projects for different founderis like Tsmc, GlobalFounderies, Intel, Qualcomm, in nodes from 22nm ultra-low power to 0.13 (μm) for custom IPs and system-on-a-chip (SoC) development.
• Deep understanding of Semiconductor Lithography Process and issues such as STI, LOD stress effects, Matching structures, MultiGuardring deep NWELL insulation structures, Latchup, Electromigration, IR-drop and Antenna issues.
• Versatile in troubleshooting with Calibre (LVS, DRC, ERC, PEX), Dracula, Cadence Virtuoso Wire Assistant and R3D for current flow analysis.
• Fluent in parasitics analyses, antenna issues, metal filling and density distribution.
• Skilled in several types of 2D/3D CAD software and CNC/CAM programming knowledge.
• Coached several junior eng. In layout methodology. - Willingness to develop new skills and a fast pace learner.
• Mechanic and Electronic background knowledge.

IC Mask Design specialization in Very Deep Submicron Layout.