Daniel Moral Luque

Computer engineer focused in low-level systems engineering and digital system design/FPGA.

Embedded Software/Hardware Engineer - 5G PHY layer at Universidad de Málaga, Dept. of Computer Architecture (Vodafone Project) (2026-03 – Present)

• FFT hardware accelerator (FPGA & ASIC): Designed and implemented modules, features and testbenches for a reconfigurable, pipelined SDF-DIF FFT IP core in SystemVerilog, aiming intelligent 5G and 6G applications.
• Integrated said IP core into a high-performance Alveo U55C UltraScale+, enabling communication between a C++ XRT host application and the FPGA through HLS DMA/AXI PCIe interconnect.
• Automated Vivado and Vitis build, packaging, execution and consistency validation flows using TCL, Python, Bash and Make scripts.
• Collaborated with microelectronics design partners digital IC engineering and verification teams.
• gNB PHY layer optimization (RISC-V): Increased the global gNB throughput by a 6x factor by optimizing physical layer modules leveraging RVV 1.0 intrinsics in a Spacemit K1 platform.
• Increased the LDPC decoder and channel precoder throughput by up to 33x and 38x respectively.
• Reduced the energy usage per bit by up to 85% in a complete gNB deployment.

MSc in Electronic Systems for Intelligent Environments – Universidad de Málaga (2026-09 – 2027-07)

BSc in Computer Engineering – Universidad de Málaga (2022-09 – 2026-07)