FPGA Design Intern - cellXica - Cambridge, England
(2026-07)
LTE software-defined radio platform, Zynq UltraScale+ RFSoC
- Designed sig_gen, a Verilog RTL accelerator emulating an LTE UE transmitter, streaming pre-computed uplink waveforms out of DDR4 in real time to automate 3GPP TS 36.141 clause 8 PUSCH throughput conformance testing of base-station receivers
- Implemented arbitrated read and write state machines over a shared 128-bit DDR4 memory interface, reverse-engineering the undocumented bus protocol from RTL source
- Replaced the fixed input buffer with a FIFO to decouple the incoming packet stream from bursty DDR4 access
- Built a simulation testbench with a stubbed memory model and file-driven stimulus, catching bus-protocol defects before hardware bring-up, then verified the datapath end to end on hardware by round-tripping data from host software through external memory and back
- Generated 3GPP-compliant PUSCH uplink waveforms in MATLAB (FRC A3-2, four redundancy versions across ten subframe positions) with fixed-point I/Q conversion to the platform's 16-bit sample format
- Integrated the module into an existing multi-platform FPGA design and worked in Vivado through synthesis and implementation, interpreting utilisation, timing and RAM-inference reports to confirm the design mapped as intended
Electrical Engineering Intern - Burns & McDonnell - London, England
(2025-07 - 2025-08)
- Worked on data centre design with the electrical team, hosting high performance compute and AI infrastructure
- Reduced manual team effort by 20+ hours by developing a script in Python to automate relabeling of engineering drawings following a naming convention change
