Rohit Wadke

Silicon Validation Engineer with hands-on JTAG/TAP architecture (IEEE 1149.1), and ATE based post-silicon debug experience from a discrete GPU project at Intel, working closely with DFT teams. Proficient in Verilog/SystemVerilog RTL debug (VCS, Verdi) and in Python, Perl and TCL automation. Seeking move into DFT engineering role.

Test and Validation Engineer at Amazon Robotics (2024-04 – 2024-12)

• Led time-study analysis across three robotics system deployment pipelines, establishing baseline metrics and identifying and resolving bottlenecks in the end-to-end deployment process.
• Proposed and implemented process-level optimizations that reduced deployment time by ~5–10%
• Designed and implemented a Python-based analysis tool to automatically quantify shelf-loading throughput on industrial hoists, eliminating manual counting and improving data accuracy.

Silicon Validation Engineer at Intel (2021-10 – 2023-10)

• Owned Pre-Silicon Reset Validation for a discrete GPU die, contributing to the successful validation of its functionality.
• Developed python-based automation to generate 50+ reset flows significantly improving validation coverage, repeatability and debugging. Version-controlled this automation script using Git/GitHub
• Established a test plan structure and review standards, setting consistency across validation deliverables
• Built a BASH automation to launch and manage simulation runs, reducing debug turnaround time by ~10% and enabling higher parallelism during failure analysis
• Led reset validation across pre-silicon RTL models, driving validation from test planning through execution
• Executed post-silicon test programs on ATE (HDMT testers), generating schmoo plots to characterize voltage/frequency margins and support debug.
• Designed and executed validation tests leveraging TAP / JTAG (IEEE 1149.1) architectures.
• Debugged RTL models using Synopsys VCS and Verdi, correlating waveform behavior with architectural expectations.

Functional Design and Integration Engineer at ASML (2019-01 – 2021-10)

• Played a key role in the design and integration of a wafer alignment sensor, a critical subsystem in DUV lithography
• Enhanced a core MATLAB-based analysis tool, reducing pre-shipment validation and quality checks timing by ~20%
• Developed a comprehensive test plan enabling customer to successfully ramp a new developed process on a DUV tool
• Collaborated with factory, software, and systems teams to translate requirements into robust solutions

Master of Science (MS) in Electrical Engineering – Illinois Institute of Technology (2015-08 – 2017-05)

Bachelor of Engineering (BE) in Electronics and Telecommunication Engineering – St. Francis Institute of Technology (2011-08 – 2015-06)