Senior Layout Mask Design Engineer
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Senior Layout Mask Design Engineer with 15+ years of experience in physical / mixed-signal design and chip implementation. Proficient in EDA tools such as Cadence Virtuoso XL and Calibre. Extensive experience in IP layout block design, including bandgap, DAC, ADC, PLL, oscillator, comparator, Schmitt trigger, LDO, buck converter, charge pump, HS/LS driver and flash memory. Experience in developing schematic / layout generator using SKILL script.
Solomon SystechLimited, Senior Physical Design Engineer
Jun 2025 - Oct 2025 (4.5 months)
achieving Level-0LVS cleanliness and validating bond wire integrity using PIM tools.
Nov 2012 - Dec 2017 (5 years and 2 months)
Aug 2003 – Jun 2004 (11 months)
The Hong Kong University of Science and Technology
Master of Science• IC Design Engineering • 2005 – 2007 • GGA: A The Hong Kong Polytechnic University
Bachelor of Engineering • Electronicand Information Engineering • 2001-2005 • 2nd Class Honours, Division I • GPA: 3.37