CPU Design for Test Engineer, Google Cloud

CPU Design for Test Engineer, Google Cloud Location: Tel Aviv, Israel; Haifa, Israel

Experience Level: Mid In most instances, this position requires in-person interviews as part of the hiring process. Note: By applying to this position, you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
• 4 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools.
• Experience with industry-standard Automatic Test Pattern Generation (ATPG) methods, fault modeling, and scan coverage debug.
• Experience validating Memory Built-In Self-Test (MBIST) structures and Joint Test Action Group (JTAG)/ Test Access Port (TAP) controllers.
• Experience running structural verification, debugging testbenches, or simulation tracking utilizing simulators.

Preferred Qualifications

• Master's degree in Electrical Engineering.
• Experience with the Tessent shell environment, specifically extracting Instrument Connectivity Language (ICL) networks.
• Familiarity with Silicon bring-up and validation on Automatic Test Equipment (ATE) testers, including debugging hardware execution patterns.
• Proficiency using Python or Tcl to manage complex Electronic Design Automation (EDA) design and sign-off flows.

About the Job Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them.

We keep our networks up and running, ensuring our users have the best and fastest experience possible.

In this role, you will be part of a varied team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Design-for-Test (DFT) Engineer, you will play a crucial role in DFT design, and support devices of extreme complexity to production. You will be responsible for developing flows, automation, and methodology, executing DFT activities. You will be responsible for test vectors end-to-end, from generating DFT content on complex design, debugging to coverage goals, simulating it at gate level, sign-off DFT to tapeout, and debugging Si results.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware, our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Execute activities in the design, implementation, and verification of Design for Testing solutions for Application-Specific Integrated Circuit (ASICs).
• Develop DFT strategy for array DFT, hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
• Perform ATPG, scan coverage debug and drive design fixes for coverage and quality improvements.
• Perform DFT verification at RTL and gate level.
• Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT design requirements are met and mutual dependencies are managed.

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Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company, and in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

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Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc.

Alphabet

Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.