We are looking for an architect to work on the invention and development of new SW visible CPU technologies to improve performance of SW scenarios related to memory ordering, memory coherency, multithreading, synchronization, memory safety, caching, etc.The minimal tasks of this role are:1. Modeling of new memory related architectural features in the existing CPU performance simulator2. Development of performance tests or adaptation of existing workloads to be suitable for simulation3.
Conducting performance studies for the workloads of choice either in the performance simulator or on a real chip4. Develop analysis, conclusions and recommendations based on the above activitiesThe role can comprehend much more than that depending on the skills, talent and experience of the candidate creating a career path over time. For example, to invent new instructions and mechanisms to overcome significant performance bottlenecks in these areas, refinement and further development of ideas provided by others.
Possible participation in development in additional domainsIf you want to be part of something bigger, if you are a team player with excellent communication skills and motivation to revolutionize data-center technology, youre welcome on board!Requirements: RequirementsFour or more years of experience in one or more of the following roles in the memory cluster of an Out of Order CPUs:Architecture or micro-architecture definition.Performance modeling and studies.RTL implementation.Verification of Multithreading.Education: Academic degree in Computer Engineering or Computer ScienceAdvantages:Knowledge and experience in memory ordering architecture.HW or SW Experience in inter-thread synchronization.Knowledge of the arm Instruction Set Architecture.SkillsGood verbal English skills.Good interpersonal skills.Team player.This position is open to all candidates.
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