We are looking for an excellent design engineer to join our team and build our state-of-the-art control and orchestration platform. We are looking for a highly talented and motivated person, who is a real team player and which can collaborate closely with engineers from other disciplines and quantum physicistsResponsibilities:Designing a configurable and very low-latency challenging RTLBringing the state-of-the-art FPGA to its limits with regards to logic & timing optimizationEnd2end ownership of the entire coding process (Arch->uArch->Design->Implementation)Learning system and SW requirements for proper implementation of HW-SW interface.Requirements: BSc in electrical/computer engineering or relevant military backgroundAt least 4 years of experienceProven track record in RTL coding with System VerilogExperience with System VerilogVCS, Vivado - Advantage.This position is open to all candidates.
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