SoC Design Verification Engineer, Cloud

Required SoC Design Verification Engineer, CloudAbout the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.As a System on a Chip (SoC) Design Verification Engineer, you will work as part of a Research and Development team.

You will build verification components, constrained-random testing, system testing, and drive verification closure.As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs.

You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.ResponsibilitiesPlan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertion (SVA) and industry leading formal tools.Identify and write all types of coverage measures for corner-cases.Debug tests with design engineers to deliver functionally correct design blocks.Close coverage measures to identify verification holes and to show progress towards tape-out.Requirements: Minimum qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.4 years of experience with creating and using verification components and environments in standard verification methodology.Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.Preferred qualifications:Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.Experience with verification techniques, and the full verification life-cycle.Experience with performance verification of ASICs and ASIC components.Experience with ASIC standard interfaces and memory system architecture.This position is open to all candidates.