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Verification Engineer

Technology
חברה בתחום תקשורת וסלולר
ראש העין, ישראללפני 2 שבועותעד 17.9.2026
משרה מלאה

תיאור המשרה

We are looking for an Experienced Verification Engineer for an exciting Job in its complex SoC/FPGAs, Networking and Modem verification team.Performing Verification in the most advanced verification methodologies/tools, implementing State of the Art verification for complex ASIC.We are looking for talented verification engineer which have abilities to own complex tasks on one hand and on the other hand be a team player, working with different vertical team and disciplines.What Youll Do as a Part of Your Role:Responsible for the Verification of Various IPs and top level designs.Defining and implementing the Environment architecture from scratch.Defining and implementing Test plans, coverage plans, etc.Requirements: Overall, 5+ years experience with system Verilog/Specman UVM based verificationExperience with Specman (Advantage)Deep understanding of verification concepts and advanced methodologiesExperience developing verification environments from scratchExperience with networking (Advantage)Good system and block knowledge/experience with digital communications networks and packet processing/managing such as : Parsing QOS, traffic shaping, policing, packet classification, WFQ, Ethernet synchronization - (Advantage)Understanding of verification and design practicesTeam playerGood communication skillsHands on experience in ASIC verification.Fast Learner High motivation to excel in career.Education: BS/BE/BTech/MS/ME/MTech or equivalent.This position is open to all candidates.

Keywords
Microsoft ExcelVerilogSystemverilog

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