Verification Engineer

We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building a complex verification environment from scratch, and defining and executing a test plan. In this role, you will be leading verification from A to Z and will have a critical impact on the company.ResponsibilitiesReview specifications and develop attributes, tests, and coverage plansDefine methodology and test benchesWork closely with the verification team to ensure the quality of the productBuild and maintain a smart and scalable verification environment that ties into various systemsWork with the software, design, and micro-architecture teams to understand the functional and performance goals of the products designRequirements: Requirements6+ years of verification experience, including hands-on experience building complex environments from scratchAdvanced knowledge of verification flow, SOC architecture and designExpertise in verification languages such as SystemVerilog, UVM, SpacemanKnowledge of industry standard tools, including Verilog, Verilog simulator, and debugClear understanding of constrained random verification process, functional coverage, code coverage, and assertion methodology and philosophyBachelor degree in electrical engineering or computer science, or equivalent experienceThis position is open to all candidates.