Verification Engineer

We are looking for a Verification Engineer who embodies ambition and positivity, who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfil the evolving needs of our expanding customer base.The Verification engineer we look for will be a highly talented and motivated person, who is a real team player and can collaborate closely with engineers from other disciplines and quantum physicists.Responsibilities:Practicing the full range of verification aspectsCreating a verification environment from scratch (drivers, monitors, coverage...)VIP (DDR/PCIe/AXI) integrationDefining verification sequences via a complex control-flow constraint setSystem understanding of a full-stack product with strong HW-SW couplingReference model integrationTest plan definitionDefining verification flows and creating the proper infrastructure to support itRequirements: 3- 5 years of experience with UVM, System Verilog.Ability to ramp up verification environments from scratch.Knowledge of Verification IPs and protocols (PCIe, DDR, AXI).Good understanding of HW/SW interaction- AdvantageKnowledge in C/C++/Python/System C - AdvantageThis position is open to all candidates.