ResponsibilitiesReview specifications and develop attributes, tests, and coverage plansDefine methodology and test benches.Work closely with the verification team to ensure the quality of the productBuild and maintain a smart and scalable verification environment that ties into various systems.Work with the software, design, and micro-architecture teams to understand the functional and performance goals of the products design.Requirements: 6+ years of verification experience, including hands-on experience building complex environments from scratch.Advanced knowledge of verification flow, SOC architecture and design.Expertise in verification languages such as SystemVerilog, UVM, Spaceman.Knowledge of industry standard tools, including Verilog, Verilog simulator, and debug.Clear understanding of constrained random verification process, functional coverage, code coverage, and assertion methodology and philosophy.Bachelor degree in electrical engineering or computer science, or equivalent experience.This position is open to all candidates.
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