VLSI Verification Engineer

We are looking for a VLSI Verification Engineer to join the ride as we spearhead the next revolution in electronics!ResponsibilitiesDevelop, debug, and maintain verification environments and testbenches using SystemVerilog and UVM.Analyze simulation results and waveforms to identify, isolate, and root-cause bugs in design or testbench code.Define, track, and analyze code and functional coverage metrics, and drive coverage closure on assigned blocks.Own the verification of assigned IP blocks or features end-to-end, from test planning through sign-off.Collaborate with the design team to clarify specifications and confirm verification completeness.Escalate complex or ambiguous issues to senior engineers when needed, and incorporate their feedback to sharpen debug skills over time.Participate in code reviews and team knowledge-sharing sessions to build best practices and technical depth.Requirements: RequirementsB.Sc. in Electrical/Computer Engineering, Computer Science, or a related field.1-2 years of experience in VLSI verification.Working knowledge of SystemVerilog and UVM fundamentals .Basic understanding of digital design and verification concepts (RTL structure, testbench architecture, simulation flow).Strong problem-solving skills, curiosity, and eagerness to learn new tools and methodologies.Detail-oriented approach and solid communication skills; comfortable asking questions and collaborating within a team.AdvantagesBasic Python skills for scripting and test automation.Familiarity with Git or other version control systems.Hands-on experience with simulation tools such as VCS, Xcelium, or Questa.Understanding of coverage concepts (code coverage, functional coverage).Familiarity with common bus/interface protocols (e.g., AXI, APB, I2C, SPI).This position is open to all candidates.