Chani Kraus

A sharp, highly analytical Hardware Verification & Software Engineer (GPA 97) with a deep understanding of digital systems, computer architecture, and object-oriented programming. Proven capacity for rapid independent learning, technical ownership, and mastering complex methodologies from scratch. Combines robust software engineering capabilities with hands-on expertise in industry-standard hardware verification lifecycles.

Hardware Verification Engineering Practicum (SystemVerilog / UVM) - The College of Management

• Built, configured, and debugged complete Universal Verification Methodology (UVM) environments from scratch, mastering UVM Factory, Config DB, and core components (Drivers, Sequencers, Monitors, and Agents).
• Verified digital logic designs at the Register Transfer Level (RTL) using Verilog and SystemVerilog, ensuring strict adherence to functional specifications.
• Developed robust test sequences and virtual sequences to implement targeted and constrained-random stimulus, effectively uncovering corner-case design bugs.
• Implemented dynamic UVM Scoreboards and Transaction-Level Modeling (TLM ports/analysis ports) for automated data integrity verification.
• Defined, wrote, and analyzed Functional Coverage models and cross-coverage metrics to identify verification holes and drive projects toward full coverage closure.
• Executed simulations and interactive debugging (waveform analysis) within Linux/Unix environments, utilizing Python scripting to automate verification flows and maximize efficiency.

Software Engineering Diploma - Computer Organization & Architecture, Digital Systems, Embedded Systems, Real-Time Systems, Operating Systems, Assembler, and Advanced Algorithms - The College of Management (2023 - 2026)