RTL Design Engineer

Description:

Our client is looking for an RTL Design Engineer to join their team. This is a direct and permanent opportunity.

Job Description:

We are looking for an experienced RTL Design Engineer to develop high-quality RTL, drive IP/subsystem integration, and ensure design readiness through rigorous quality checks including Lint, CDC, RDC, synthesis, and handoff validation.

Skills Required:

• Strong experience developing synthesizable RTL using Verilog/SystemVerilog.
• Experience working on complex digital IPs and SoC subsystems.
• Ability to translate architecture specifications into scalable microarchitectures.
• Experience integrating IPs and AMBA interfaces, including:
• AXI4, AXI4-Lite, AHB, APB
• Strong understanding of RTL coding standards and design methodologies.
• Experience with RTL reviews and design quality assessments.
• Hands-on experience with:
• Lint, CDC, RDC
• X-propagation
• Synthesis
• Structural checks
• Design-rule checks
• Experience with clock/reset handling, address mapping, and configuration.
• Strong debugging and problem-solving skills.
• Experience developing automation, dashboards, and quality metrics is an advantage.

Responsibilities:

• Develop RTL from architecture interpretation through design handoff.
• Perform IP integration, clock/reset handling, address mapping, and configuration.
• Conduct detailed RTL reviews and quality assessments.
• Identify and drive closure of functional, structural, and methodology issues.
• Analyze and resolve Lint, CDC/RDC, X-propagation, synthesis, and structural violations.
• Collaborate with architecture, design, and verification teams.
• Ensure RTL handoff readiness through clean signoffs.
• Ensure protocol compliance and register-spec alignment.
• Validate clock/reset architecture.
• Develop and enhance design automation and quality methodologies.
• Build automated checks, regression analysis, dashboards, and team-level quality gates.

Key Technologies:

• HDL: Verilog, SystemVerilog
• Protocols: AXI4, AXI4-Lite, AHB, APB
• RTL Quality: Lint, CDC, RDC, X-Propagation, Synthesis
• Design: IP Integration, SoC, Digital Design, Clock/Reset, Address Mapping
• Automation: Regression, Dashboards, Quality Metrics