GPU Computing & HPC Systems Engineer
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HPC algorithm specialist with a proven record of designing and implementing high-performance parallel graph algorithms at billion-edge scale. Published at IEEE IPDPS (3 papers in 2026), Euro-Par, ICPP, HiPC (all CORE A venues). Achieved up to 900× speedup over state-of-the-art baselines; Euro-Par 2025 paper runners up for Best Paper Award.
Holds a US Patent on a high-concurrency in-memory database. Masters thesis explicitly recommended for the "Best MS Thesis" award. Deep expertise in CUDA kernel optimisation, PRAM algorithm design, out-of-core GPU computation, and dynamic graph processing.
Systems Engineer — Slingshot Interconnect (SDE-I) - Hewlett Packard Enterprise (HPE) - Bengaluru, India
(2025-02)
M.S. (Research) - Indian Institute of Technology Tirupati