Abhinav Davala

VLSI engineering student with hands-on experience in RTL design, digital system design, and ASIC flow (RTL-to-GDSII). Proficient in Verilog, synthesis, place and route (P&R), static timing analysis (STA), and functional verification using Cadence and Vivado tools. Interested in digital design and ASIC development roles.

Remote Project Intern - Prov Logic - Remote

(2025-02 - 2025-04)

Worked on RTL design and implementation of digital systems using Verilog.

• Designed and implemented a 32-bit MIPS processor with pipelining architecture.
• Developed and verified a 7-bit Hamming decoder for error detection and correction.
• Successfully simulated and validated both designs using Xilinx Vivado.

BTech - Electronics and Communication Engineering - Manipal Institute Of Technology (2023 - 2027)

Senior Secondary - Narayana Junior College (2021 - 2023)

10th Grade - Narayana Olympiad School (2020 - 2021)