Project Engineer (IC Role) - Synopsys India Pvt Ltd - NOIDA
(2024-04)
Currently working as a Project Engineering Manager For SerDes PHY IP for PCIe6
- Working as an Individual contributor for SERDES PHY IP Delivery
- Defining project delivery timelines as per the CQF and customer Specification
- Defining scope to meet customer needs in a timely manner
- Defining Project Planning, schedule delivery, budget, resources, deliverables, and risk management
- SOW (Statement of Work) overview and Planning of the resources
- Project Plan creation in Microsoft Project Planning tool (MPP), Gantt Charts
- Multiple tool usages- VC, PHY PPM Dashboard, Clarity, CQF, QTIP, JIRA, Confluence One note
- Collaboration with the different team members for deliverables-DIG/ANA/PD/DOC/QA etc
- Weekly Cross Team Meeting across globe with different stake holders for project execution
- Providing technical training to the internal teams
- Helping in project executions from RTL to GDSII complete delivery
- Collaboration with the RnD and different stake holders
- Risk register maintenance and follow up for further updates
- Set deliverable priorities, and keep the team focused on goals
- Ensure smooth hand offs to downstream teams and customers
- Filing JIRAs to streamline the process
- Follow up Project Progress with JIRA dashboard and confluence
- Tracking program milestones and critical KPIs such as power, cost and performance
- Weekly dashboards Update, close checklist items, and provide status updates to stakeholders
- Lead execution reviews, technology/IP/process reviews
- Pre and Post QA Release follow up with the project delivery team
- Responsible for the on-time project delivery, product quality and cost
- Maintain comprehensive documentation of project plans, progress reports, and post-delivery evaluations
Advanced Product Engineer- Questa Lint/CDC / QA / Product Validation Lead -Precision FPGA and Oasys ASIC synthesis Tool - Siemens EDA (Mentor Graphics) I Pvt Ltd - NOIDA
(2012-10 - 2024-03)
Worked as a Product Engineer for Questa Lint/CDC tool. I had also performed QA Lead for Precision and Oasys synthesis Tool and Project management using Agile, JIRA.
- Assisting field and AE teams by offering support on Questa static verification tool, Lint and CDC tool
- Creating testbench, Verification of Modules; Assertion based Verification
- Formal Equivalence Check Using Formal Pro for customer designs
- Providing technical support to the customers in their ASIC and FPGA development design cycle
- Supporting Industry Standard checks like STARC, RMM, DO-254 and Custom Checks
- Lint FPGA Design flow automation and implementation
- Helping in collateral development like documentation support, developing AE training material, AppNote creation, Field Training etc
- Product Management for Synthesis tool and HLS tools using JIRA
- Helping in the release cycle or the product development
- Product Validation Lead for Precision and Oasys Synthesis tool
- Debugging of RTL designs, creating test benches to run simulation, Coverage checks
- Analyzing daily regression run for different builds in Mainline and Trunk
- Culprit analysis on different builds, bug analysis and fixing, tracking issues and reporting to RnD
- Automation of scripts using Bash, Shell, Python, TCL etc
- Automation of regression analysis using Jenkins and Scripting
- Implementation of unit testcases for issues debugging using HDL
- Product release testing, (Check point, License testing, Regression)
- Newly added feature testing for the latest product release
Senior Project Engineer - Wipro Technologies - Bangalore
(2011-07 - 2012-09)
Worked as a senior project engineer for different client projects.
- Design and implementation of Power Management (PMIC) IC for TI (ODC project)
- Writing RTL code with the LRM based coding standard
- Performed RTL coding in Verilog/VHDL for the dedicated Module, testbench Verification, Assertion based verification, Formal Verification using formal pro, Synthesis, STA, checking CDC issue and perform Lint checks for the same
- Collateral development of the work for future references
- Group of 4 members were deployed to the project
- I was working on one major module i.e. Coulomb Counter
- Worked on FPGA prototype module; Implementation of baseband modulation of transceiver 802.16e - WiMAX
Application Engineer (Xilinx and Mentor Graphics Products) - CG-CoreEL (I) Pvt Ltd - Bangalore
(2009-04 - 2011-06)
Worked as an Application Engineer for Xilinx and Mentor Graphics Tools
- Providing technical support to the customers those were using Xilinx FPGAs (Spartan, Virtex) and Mentor Graphics tools in their projects (RTL 2GDSII flow)
- Providing demos to the customers, onsite training, and FPGA prototyping project support
- Hands on training to Xilinx and Mentor tools usage and support
- Simulation of RTL design using testbench approach, Formal Verification, Static Verification etc
- Creating training materials, documentation, Lab and PPTs materials for customers
