Akshara Davanapally

Final year Electronics and Communication Engineering student specializing in RTL Design and Digital Design. Hands-on experience with Verilog HDL, FSM design, Clock Domain Crossing (CDC), and FPGA implementation. Seeking a Front-End RTL / VLSI Design Engineer role to apply expertise in synthesis and functional verification.

Research Intern at IIIT Sri City (2026-05 – 2026-06)

• Built a neuromorphic "e-nose" in NGSpice mimicking smell detection, converting gas levels into timed electrical pulses (ΔT) rather than voltage readings.
• Used event-based sensing via PWL data to react only when signals change, optimizing efficiency.

VLSI Intern at Sense Semiconductors and IT Limited (2025-05 – 2025-06)

• Cold Storage Regulation: Designed a 6-state FSM in Verilog to automatically manage temperature.
• Tested and confirmed the design on an Artix-7 FPGA board for real-time responsiveness.

Bachelor of Technology in Electronics and Communication Engineering – Rajiv Gandhi University of Knowledge Technologies, Basar (2023 – 2027)

Pre-University Course (PUC) – Rajiv Gandhi University of Knowledge Technologies, Basar (2021 – 2023)

Secondary School Certificate (Class 10) – Carmel Convent High School, Mancherial (2011 – 2021)