Senior Program Manager at Microsoft (2024-03 – Present)
Working on Cobalt 100 and 200 (Arm-based CPU) data center compute server platforms/blades
- Associated with Firmware System engineering team(FSE) of 15+ engineers working across multiple firmware components.
- Closely collaborate with the teams Firmware SoC development teams (HSP, Accelrator,UEFI, RAS, Telemetry etc), FPGA, PMO, OS teams, IFWI Integration, Silicon HW & platform workstreams (open BMC, Rack manager, Manticore etc) to understand their scope and milestones
- Work with the FSE engineering teams to define their test strategy for cluster deployments releases, Define the scope of the FSE validation across multiple firmware components of ARM Platforms including BMC-SOC communication, Power and thermal management, Inband and out of band (OOB) firmware update from BMC and RSCM, firmware security (secure boot, attestation), RAS (OS and FW first RAS scenarios),SMBIOS, Crashdump, Telemetry and Workloads
- Experience in coordinating activities between HW, FW and SW, Lab Teams, problem-solving, communication, and collaboration skills.
- Involve in reviewing the Validation test plans (such as Telemetry, Workloads & VM, BMC, Security modules, Accelerator etc) with the partner teams like FW SoC development, silicon and Platform.
- Working closely with the Directors, Solution Architects, Engineering managers and Validation Leads across the domain such as BMC, FPGA, Windows and Linux OS teams, Telemetry, Security etc.
- Regular reporting to executives about the health of the program includes progress of the test coverage, Bug indicators, Risks and mitigation plans to meet the internal and external milestone for Manufacturing team and cluster deployments for engineering group.
- Experience in Azure Devops for the Sprint planning, Dashboard, Capacity planning for milestones, Tasks and Test Planning, Bugs tracking, Pipeline execution for automation tests (functional, Resets tests and Long Workload stress tests), Release Artifacts across multiple compute programs.
- Experience with AI coding tools (GitHub Copilot) and integrating them to test workflows.
- Experience in working with Data Center Business Unit for launch cluster plans ( Rack setup from Manufacturing team, Docking into Datacenter, Hand over to EG for Workload Deployment), collaborate with Program managers and Engineering teams to determine the customer launch (Preview launch and general availability)schedules & releases.
Senior Validation Program Manager at Intel (2021-12 – 2024-03)
Worked on the SmartNIC FPGA 200G network card requirement for the Data center BU, the objective of the network cards is to offload the server CPU load by 10-15%.
- Work with the PMO, HW & SW Engineering team to define the scope of the FPGA SmartNIC- accelerator cards for several workloads like traffic & storage, schedules plans and deliverable tracking for the milestone.
- Working closely with the IP Design (PCIe, OVS, VirtIO, Memory and HSSI subsystem), Sub system Validation, RTL integrations teams (Shell), FPGA software stack and Platform software Linux teams to drive the milestone features are enabled, make sure entrance criteria meet, defining release cadence, Validated CI/CD and delivered to Validation teams as BKC.
- Working closely with the Directors, Solution Architects, people managers and Validation Leads across the domain such as PCI, Memory, OVS, Linux SW teams, Telemetry, networking, Security etc.
Program Manager1 at AMD (2015-06 – 2021-12)
Analyzing the software requirement for the AMD consumer graphics cards, APU based platforms and define the scope and schedule for the driver releases.
- Experience in defining the process for projects deliverables by using different tools to make sure the engagement is improved across the software Development and QA teams.
- Work with cross functional teams including Design, Development and Customer Engineering for prioritized problems. Prioritize requirements that define product roadmap, and constantly improve quality in the product.
- Worked on Consumer-laptop market, Gaming, OpenCL workloads and Enterprise compute on both software and hardware. Successfully planned and executed many commercial AMD product in CPU and GPU markets.
- Define and Prepare overall Quality report with detailed customer impact analysis, which captures the Functional, Automation, Performance and Stress & Stability reports.
- Prepare overall Quality Test report with detailed customer impact analysis, which captures the functional, Automation, Performance and Stress & Stability test reports.
Technical Leader at SMARTPLAY, Qualcomm (2013-03 – 2015-06)
- Involved in porting the Qualcomm specific components to the Tizen platform, which involves in wiring the makfile.am, bitbake receipe files based on open embedded Linux.
- Ported the Qualcomm Camera stack to Tizen and fine tune some of the features specific to Tizen platform.
- Ported the Securemsm modules like QSEECOM, TZservices, DRM and playready modules from Android to Tizen mobile platform and performed the qseecom, playready and widevine and performance tests.
Technical Leader at TELECA (2008-12 – 2013-03)
- Worked in SWAT team known for fixing and supporting all type of Complex issues in customer Android mobiles and Tablets. The issues such as Boot time optimization, Performance issues in System side Kernel, Application, Middleware and framework.
- Involved in addressing the issues in the Camera Sensor driver and Camera middleware (HAL).
- Worked as on-site coordinator role between Nokia, Finland and ODC in Bangalore. Worked in a team of twenty for Maintenace of Fremantle Applications.
- Maemo and Fremantle Architecture, Used the scratchbox environment for Cross compiling and used scripts for automation to start the platform.
Senior Software Engineer at AZINGO (2008-06 – 2008-11)
- Configured and Compiled Linux Kernel 2.6.21 version for selinux support.
- Modified the open source libselinux-2.0.65 library to the AZINGO platform.
- Created ROOTSTRAP with the above modified selinux libraries and some of the busybox utilities for selinux
Software Engineer at CMC, Ericsson AB (2006-09 – 2008-04)
- Responsible for importing TIP stack delivered by Ericsson Denmark to Clearcase.
- Maintenance of the Ericsson UPDDD. ( Intel PCI Gigabit Ethernet Controller)
- Written scripts to automate the testing and code generation and Release responsible for Product to I&V Team.
System Engineer at Linkwell Telesystems (2005-08 – 2006-09)
Worked in a team of five for the firmware development of software POS modules.
- Developed USB tool and USB driver for the product (POS) to download the required images into the product. Using GNU tool chain for ARM processor using the busybox version 1.00
- Implement SSL (Secure Socket layer) support libraries in the product and written networking applications by using TCP/IP Socket Programming and SSL API's.
