ECE graduate pursuing M.Tech in VLSI design, aiming for a career in VLSI Design Verification. Familiar with SystemVerilog, UVM, and digital design fundamentals.
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Aspiring Engineer with a strong foundation in Verilog, System Verilog, UVM and experience in Optical Wireless Communication(OWC) projects. Skilled in adapting to new technologies and environments, with a focus on applying technical knowledge to drive team success. Eager to leverage technical skills and continuous learning to contribute to innovative development projects.
B.E in ELECTRONICS AND COMMUNICATION ENGINEERING – SIR M.VISVESHWARAYA INSTITUTE OF TECHNOLOGY (2021-01 – 2025-12)
SENIOR SECONDARY (XII) in SCIENCE – MES CHAITANYA PU COLLEGE (2019-01 – 2021-12)
SECONDARY (X) – SHRINIKETANA SCHOOL (2018-01 – 2019-12)
Mtech in VLSI Design and Embedded System – RAMAIAH INSTITUTE OF TECHNOLOGY (2025-11 – 2027-08)
