ASIC Design Verification Engineer
Self-Motivated, Result Oriented, Creative and Quick Learning ASIC Design Verification Engineer with 5 years of total IT Experience. IP and SOC verification with very good experience in creating test cases, test plans, writing test benches in Verilog and System Verilog.
Experience in finding bugs in the design and fixing them. Architected class-based verification environment using system Verilog. HDL module design, Simulation/Synthesis/Optimization of HDL modules in design tools like Synopsys/Cadence/Xilinx/ModelSim.
Have exposure to DFT (BIST, Boundary Scan, etc.) and Back End (Physical Design) Software Tools for Back-end Design like DRC, LVS, ERC, Floor Planning, Optimizations for Power and Area till Fabrication of the Physical Chip and after that Emulation with Test vectors and Sign off from the ASIC Design Cycle.
Script files using PERL and Shell, to link the Test bench along with the DUT with the Test Environment. Well versed with protocols (High Speed Bus Protocols (AXI 4.0), Cache Coherency Protocols, etc.), Design and Verification. Knowledge on SOC Verification and creating test environment for Verification of SOCs.
Micro code module for RISC CPU, MIPS 32-Bit pipelined processor and Bi-directional bus using FPGA, Schematic Capture/Simulation of MOS Op-Amp in P-Spice with current mirror. Complete and comprehensive knowledge of Multicore processor architecture and Multiprocessor architecture. Complete knowledge of different cache coherency protocols for Multiprocessor system architecture. Excellent experience in organizing projects, writing technical reports and problem solving.
Assistant Professor in CSE Department - Parul University
(2024-04 - 2024-10)
Aerospace Hardware Senior Specialist - NISG (NATIONAL INSTITUTE FOR SMART GOVERNMENT) - Bangalore
(2023-10 - 2024-01)
Client: DRDO, Bangalore. Department: CASDIC (COMBAT AIRCRAFT SYSTEM DEVELOPMENT AND INTEGRATION CENTRE). Project Name: ATMARAKSHAK. Development of Key Functional Features of the Aircraft.
Engineer - Expleo - Bangalore
(2021-11 - 2021-12)
Project Department: AVIONICS. Project Client: Mercury Systems, Geneva, Switzerland. VIP Qualifying Assessment of AVIONICS IP VIPs. There were about 8 VIPs needed to be assessed given by the Client Mercury Systems.
Engineer V2 Grade - Aricent - Bangalore
(2018-05 - 2018-07)
Hired as ASIC IP Verification Engineer for ASIC IP Design Verification Projects. Interviewed by 2 clients, 2 rounds each. The company management was cutting workforce from the company due to company policy, happened to be one of them and got relieved by company management on 27 July 2018.
Lead Engineer - HCL - Noida
(2017-04 - 2017-08)
Project Name: SRAM Memory Controller Verification.
Client Name: Renessa, Japan. The project was to verify the SRAM Memory Controller. The verification IP, AXI VIP, was already bought from Synopsys. Led a 5 member team to verify the SRAM Memory Controller with each allocated around 11 test cases to develop. Team members were supposed to develop the Scoreboard (Checker) and the Coverages module for the test bench. Given 11 test cases to verify the operations (Functionalities) of the Control Registers of the Memory Controller. Communicated with Synopsys Inc. concerned person for the AXI VIP for the development of project work to make the test bench compatible to verify the SRAM Memory Controller. Verified internal registers called Control Status Registers. First test case was to verify the toggling of the CSR last bit that toggle after each successful completion of the transaction/s. Remaining 10 test cases were about the verification of the other features of the Memory controller using Control Registers.
Systems Engineer - Wipro - Bangalore, India
(2011-06 - 2012-01)
Project Name: NSN-GAIA.
Client Name: Nokia – Siemens Networks. NSN (Nokia Siemens Networks) - GAIA (Generic Air Interface ASIC) is a chip of interface between an Optical-Fiber and Air. The communication signals of 7 different carriers' types, like CDMA, LTE, etc., coming from the Optical-Fiber get stored according to the carrier type in the memory first and later get processed inside the GAIA chip and later transmitted in the Air for next processing on the receiving end. Verified the first two modules that first identifies the carrier type and stores the data (information) after separating the payload data from the ID of the carrier types inside the designated area of the memory according to the carrier type. The GAIA chip verification was successful using Verilog Test Bench as well as SV test bench both. Exhausting testing was done for all the combinations of the different test vectors using System Verilog Test bench. The corner cases were verified by Verilog Test bench identifying separately. Both the test results, Verilog and System Verilog, were incorporated and final design was released to the Customer.
Assistant Engineer – VLSI Design - Silicon Interfaces - Mumbai
(2009-07 - 2009-07)
Project Name: ASIC Verification. The project work was about to be allocated.
VLSI Design Engineer - Embassys - Ahmedabad
(2007-10 - 2008-04)
Project Name: Device Driver Development. Client Name: Embassys. Embassys is an Embedded and VLSI training and Placement company.
Printed Circuit Corp - USA
(2006-10 - 2006-11)
Delasoft - Delaware, USA
(2007-01 - 2007-04)
AK Systems - Baroda
(2005-11 - 2006-07)
Lecturer - Sigma Institute of Engineering - Baroda
(2012-07 - 2014-12)
Was promoted as a Head of the Department of Electrical and Electronics Engineering.
Instructor/Project Guide/Lecturer/Assistant Professor - DD Institute of Technology - Nadiad
(2005-03 - 2005-11)
Instructor/Project Guide/Lecturer/Assistant Professor - DD Institute of Technology - Nadiad
(2001-01 - 2001-06)
Instructor/Project Guide/Lecturer/Assistant Professor - Netvision India Private Limited - Vadodara
(2000-05 - 2000-11)
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