Balasundaram S

Having 8.6 years of experience in ASIC front End Design Verification and 2 years of experience in Embedded and Telecommunication. Proficient in developing test plan, test creation, block and chip level test bench environment development, scoreboard, functional coverage, Assertion and regression management to verify RTL. Experienced in building verification environments from scratch.

Very good understanding of verification flow with C, System Verilog and UVM. Experienced in SV-UVM based verification environment. Experienced in SOC level/full chip integration. Understanding of ARM Architecture verification.

Experienced in protocols: DDR4, DDR5, MRDIMM, AMBA AHB, AMBA APB, AMBA AXI, MIPI I3C.

Staff Engineer - Synopsys India Pvt Ltd

(2022-08)

DDR IP Design verification with AI Driven Debug capabilities using Copilot ai, Cursor ai with Verdi Assistant. Verifying DDR4/DDR5/MRDIMM Gen2/Gen3 STD Product controllers, PHY and DRAM using SV and UVM-based environments.

• Verifying DDR4/DDR5/MRDIMM Gen2/Gen3 STD Product controllers, PHY and DRAM using SV, UVM-based environments
• Taken the ownership of Scoreboard for new future enhancements and fixing SCB related signatures for multiple products
• Taken the ownership of coverage and created directed test cases for uncovered functional coverage as per the spec requirements
• Created directed and constrained-random test cases for protocol compliance
• Used checkers by SVA assertions for protocol checks
• Debugging and analyzing the critical bugs using Synopsys Verdi Assistant, nWave, FSDB. Tracking the issues in JIRA dashboard
• Plan and drive the team for customer project closures on delivery time. Prepare the team Quality Audit as per Audit guidelines

Senior Verification Engineer - Mirafra Technologies

(2022-03 - 2022-08)

Chip Level Verification of SOC for Western Digital. The VEGA architecture has different integration & SOC verification.

• Created directed and constrained-random test cases for protocol compliance
• Debugging and analyzed the critical bugs

Technical Lead - Sankalp Semiconductor Pvt Ltd (HCL Technologies)

(2018-03 - 2022-02)

Technical Lead role spanning multiple client projects including ST-Microelectronics, Microchip, TI, ARM, and L&T-Intel.

Verification Engineer - ST-Microelectronics (Client at Sankalp Semiconductor)

(2021-12 - 2022-02)

Chip Level Verification of SOC. The Cobra architecture has different Cobra design phases for front end integration & SOC verification.

• Worked on Gate level simulation, debugging the failure test cases

Verification Engineer - Microchip (Client at Sankalp Semiconductor)

(2021-03 - 2021-12)

Block Level Verification of IP MIPI I3C. The Joshua Tree is a family of low power integrated and configured to communicate with the system host through one of three host interfaces: I3C, USB, SPI or I2C.

• Integration of VIP and RTL in block level TB environment
• Integration of RAL and memory model in block level
• Initial Environment bring up for Single DUT Master with Multiple Slaves
• Developed the block level TB verification environment to verify RTL
• Developed and verified the sequences and test cases as per RTL
• Developed the TB verification, test case plan, scoreboard and functional coverage and assertion as per RTL requirements

Verification Engineer - TI (Client at Sankalp Semiconductor)

(2020-10 - 2021-02)

Chip Level Verification of Subsystem. The Cortex-M0+/M33 processor is an energy-efficient processor with a very low gate count. Intended for micro-controller and deeply embedded applications that require an area-optimized processor.

• Developed and verified the sequences and test cases as per RTL
• Generated .init file to load backdoor and access from front door and verified the ROM
• Developed the code execution from SRAM and FLASH
• Developed the verification plan for VBUS generic Interface

Verification Engineer - ARM (Client at Sankalp Semiconductor)

(2019-07 - 2020-08)

ARM V8A Cortex Processor Architecture Validation. This project involves An architecture specifies how a processor will behave, for example what instructions it has and what the instructions do.

• Worked on different suites enhancement
• Debugged different failure signatures form regression results and file the JIRA
• Validate each Exception levels and Execution states
• Validate the physical and virtual addresses

Verification Engineer - L&T-Intel (Client at Sankalp Semiconductor)

(2018-05 - 2019-04)

Chip Level Verification of SOC. This NSG project involved verification of NOC which connected with Master and slave devices.

• Ported test cases in DUT side to verify NOC Level Environment
• Developed the TB verification, test case plan, functional coverage and assertion as per RTL requirements
• Developed the IO's connectivity check from chip level to block level using perl script
• Developed and verified the sequences and test cases as per RTL requirements

Internship - Clarozon Technologies

(2017-06 - 2018-03)

Block Level Verification of RTL by using Verification IP's - Verification of AMBA AHB

• Integration of VIP and RTL in block level TB environment
• Developed the TB verification, test case plan, scoreboard and functional coverage and assertion as per RTL requirements
• Initial Environment bring up for Single DUT Master with Multiple Slaves
• Developed the block level TB verification environment to verify RTL
• Developed and verified the sequences and test cases as per RTL

Engineer - TCTSL

(2016-06 - 2017-06)

Testing & Quality Control Engineer - Helios Solutions Ltd

(2011-04 - 2012-05)

Master of Engineering - VLSI DESIGN - Anna University Regional Centre, Coimbatore, Anna University Chennai (2013 - 2015)

Bachelor of Engineering - Electronics and Communication Engineering - Sri Nandhanam College of Engineering and Technology, Tirupattur, Anna University Chennai (2007 - 2011)

HSC - Ramakrishna Higher Secondary School, Tirupattur (2007)

SSLC - Government Garden High School, Tirupattur (2005)