Battinapati Durga Manohar

Design Verification Engineer with strong foundations in digital electronics, RTL design, and SystemVerilog/UVM methodology. Skilled in architecting reusable UVM testbench environments from scratch — sequencers, drivers, monitors, scoreboards, protocol checkers, SVA assertions, and functional coverage models — for AMBA-based SoC designs (AXI4, AHB, APB). Proficient in RTL coding, constrained-random verification, SoC connectivity validation, regression debugging, waveform analysis, bug tracking, coverage closure, and transaction-level verification.

Experienced in verification planning, simulation/report generation, and working with industry-standard EDA tools including Synopsys VCS and QuestaSim. Strong analytical, debugging, and cross-functional collaboration skills with the ability to contribute effectively to high-quality semiconductor design and verification projects.

Design Verification Trainee - Maven Silicon

(2025-04 - 2026-02)

Advanced VLSI Design & Verification training program

• Designed and verified RTL/IP blocks using Verilog/SystemVerilog with lint-aware, synthesis-ready coding practices; performed functional verification, RTL debugging, waveform analysis, and verification closure across SoC and IP-level projects.
• Architected complete UVM-based verification environments from scratch, including sequencers, drivers, monitors, scoreboards, protocol checkers, SVA assertions, coverage models, and multi-instance VIP integration for multiple verification projects.
• Developed metric-driven verification and test plans from block-level specifications; created constrained-random testcases to validate AMBA protocol functionality, corner-case scenarios, and overall design behaviour.
• Executed regression suites, tracked and debugged simulation failures through root-cause analysis, generated verification reports, and achieved functional/code coverage closure while collaborating in multi-project VLSI verification environments.

AI-Embedded Systems & Robotics Intern - RoboCoupler

(2025-01 - 2025-03)

• Developed embedded automation systems using ESP32 and Arduino, demonstrating ability to work independently on hardware-software integrated projects.
• Built a CNN-based plant disease detection model using TensorFlow, achieving 98% accuracy — demonstrating practical AI/ML integration with embedded hardware.
• Performed system-level debugging and performance optimisation across firmware and hardware layers, applying structured root cause analysis techniques.

B. Tech - Electronics and Communications Engineering - Vignan's Institute of Information Technology (2021 - 2025)