Physical Design Engineer | ASIC Backend | RTL-to-GDSII
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M.Sc. Electronics graduate with hands-on ASIC Physical Design exposure across 14nm and Sky130 flows. Practical experience in synthesis, SDC constraints, floorplanning, power planning, placement, congestion analysis, and PG connectivity debugging using Synopsys and open-source EDA tools. Working knowledge of STA, setup/hold analysis, CTS, and routing. Seeking entry-level Physical Design, ASIC Implementation, or Place & Route roles.
Website Tester / QA Engineer at Blue Zone Online Marketing Solutions (2023-08 – 2025-02)
M.Sc. in Electronics – Mangalore University (2022)