Deepankshi Chittora

Accomplished EDA Professional and R&D Staff Engineer with over 10+ years of extensive expertise in Physical Verification, integrated circuit methodologies, and advanced node technologies. Proven track record at industry-leading organizations including Synopsys and Cadence Design Systems, specializing in DRC, LVS, FILL, and DFM flows across sub-5nm nodes (down to 1.2nm). Recognized for strategic optimization of tool performance, foundry-to-design bridging, and developing highly efficient automation frameworks that significantly accelerate design convergence cycles.

R&D Staff Engineer (CAD) - Synopsys India Pvt. Ltd. - Hyderabad, India

(2023-11)

Core Tools & Ecosystem: IC Validator, Custom Compiler, ICV-Live, ICVWB

• Serve as a critical technical bridge between foundry and internal design teams to resolve bugs, drive enhancements, and align tool development with production requirements
• Lead DRC, FILL, LVS, Antenna, and DFM checks utilizing IC Validator for complex, high-stakes tape-outs across advanced semiconductor process technologies (1.4nm, 2nm, 3nm, 4nm, 5nm, 7nm, and 12nm)
• Develop custom internal runset deck coding configurations for leading-edge process geometry nodes
• Architect optimized physical verification methodologies and automated flows, enabling significantly faster design convergence and enhanced quality of results (QoR)
• Evaluate, validate, and benchmark tool capabilities across major version releases to guarantee robust performance and seamless customer flow deployment

Sr RD Engineer - Synopsys India Pvt. Ltd. - Hyderabad, India

(2021-06 - 2023-11)

RDII Engineer - Synopsys India Pvt. Ltd. - Hyderabad, India

(2019-04 - 2021-06)

Product Validation Engineer I - Cadence Design Systems India Pvt. Ltd. - Noida, India

(2015-09 - 2018-03)

Core Tools & Ecosystem: Quantus, Quantus FS, Shell Scripting

• Managed weekly regression operations for in-house and customer-provided designs on diverse technology nodes; engineered custom automation frameworks for execution and reporting
• Driven validation and deployment of new enhancement features for parasitic extraction (RC) mechanisms within the tool ecosystem
• Conducted rigorous root-cause analysis for complex bugs and formulated targeted technical patches or architectural workarounds for key global accounts
• Led comprehensive Accuracy QA benchmarks across advanced nodes including 40nm, 28nm, 20nm, 16nm, and 10nm to ensure structural precision

Engineering Trainee (HEP2) - Mentor Graphics (Siemens EDA) - Noida, India

(2014-06 - 2014-07)

Core Tools & Ecosystem: QuestaSim 10.3a, Verilog, SystemVerilog, UVM

• Developed robust verification test-benches using Verilog and SystemVerilog for various complex electronic ASIC designs
• Applied basic Universal Verification Methodology (UVM) concepts to design architectures
• Successfully completed design and verification projects including a 16-bit pipelined/un-pipelined LC3 Microcontroller, a UART block, and a FIFO buffer system interfaced with RAM

B.Tech - Electronics and Communication Engineering (ECE) - Rajasthan Technical University (TINJRIT) (2015)

Senior Secondary (XII) - PCMB - CBSE (2011)

Secondary (X) - CBSE (2009)