🔬 Analog Layout Engineer | VLSI Design Postgraduate | Chip Tapeout | Research Scholar I am an Analog Layout Design Engineer with 1+ year of hands-on industry experience at Semiconductor Industry, working on full-custom IC layouts across SCL 180nm and TSMC 65nm technology nodes using Cadence Virtuoso and Mentor Graphics Calibre. Currently pursuing M.E. VLSI Design at Anna University, I bring a rare combination of academic depth, real industry experience, and working silicon — having successfully completed a chip tapeout. 🛠️ Technical Expertise ▸ Full-custom analog layout — floorplanning, placement, routing, DRC/LVS signoff ▸ Parasitic optimization and layout-dependent effects (LDE) management ▸ Circuits: Current Mirrors, Differential Amplifiers, Two-Stage Op-Amps, Bandgap Reference ▸ Tools: Cadence Virtuoso (L/XL), Spectre, Assura, Mentor Graphics Calibre, Magic, Klayout ▸ Technology: SCL 180nm, TSMC 65nm, 2nm | Foundries: TSMC, SCL 🔬 Research & Achievements ▸ Research Paper — ICREACT 2024, SRM Institute of Science and Technology ▸ Full Fellowship Awardee — VLSID 2026, Pune ▸ Session Handler — Workshops on Analog IC Design, Government College of Technology, Coimbatore 🎯 Areas of Interest Analog VLSI Design · ASIC Design · Analog Layout Design · Biomedical IC Design 📩 Open to opportunities in Analog Layout Design and Mixed-Signal IC Design. Feel free to connect or reach me at anwarbadhusha4@gmail.com
