Dhruv Sachdeva

I am a motivated Verification IP Engineer with hands-on experience in developing, debugging, and enhancing UVM-based verification IPs for industry-standard protocols such as AXI3, AXI4, AXI4-Lite, AHB, and APB. At Siemens EDA, I contributed to creating detailed verification plans, implementing protocol-specific test scenarios, and automating regression flows to streamline test execution. Skilled in SystemVerilog, UVM, scripting (Python, Perl), and simulators like QuestaSim and VCS, I thrive in Linux-based development environments.

I am passionate about building robust, reusable verification solutions that ensure protocol compliance, functional accuracy, and high-quality deliverables for complex semiconductor systems.

Hands-on experience as a Verification IP Engineer, specializing in SystemVerilog, UVM, and AMBA protocols (AXI3, AXI4, AXI4-Lite, AHB, APB). At Siemens EDA, contributed to developing and maintaining protocol verification IPs, creating verification plans, implementing functional fixes, automating regression flows, and debugging multi-protocol environments. Skilled in scripting (Python, Perl), using industry-standard simulators (QuestaSim, VCS), and working in Linux-based environments.

Strong track record of teamwork, problem-solving, and delivering high-quality, reusable verification solutions.

B.Tech in Engineering Physics from Delhi Technological University (CGPA: 7.9), with core subjects including Digital Design, Microprocessor Architecture, Fiber Optics and Optics, Communication Systems, and Quantum Mechanics. The program provided a strong blend of theoretical knowledge and practical lab experience, building expertise in electronic systems, hardware design, and computational methods that form a solid foundation for protocol-based verification and semiconductor design.