Divij Jain

FPGA Design Engineer with extensive experience in protocol decode, RTL design, simulation, timing closure, and hardware validation for oscilloscope platforms. Specializing in deep protocol investigation, architectural feasibility studies, and complex bug resolution, contributing to high-performance, reliable FPGA solutions in a Linux-based development environment. Demonstrated leadership in driving protocol enhancements and ensuring precise decode accuracy across multiple communication standards.

R&D FPGA Design Engineer at Nippon Data Systems Ltd. (Keysight Technologies) (2024-09 – Present)

FPGA Design Engineer with extensive experience in protocol decode, RTL design, simulation, timing closure, and hardware validation for oscilloscope platforms. Specializing in deep protocol investigation, architectural feasibility studies, and complex bug resolution, contributing to high-performance, reliable FPGA solutions in a Linux-based development environment. Demonstrated leadership in driving protocol enhancements and ensuring precise decode accuracy across multiple communication standards.

• Worked on FPGA-based serial decode and trigger logic for oscilloscope platforms supporting protocols such as CAN, UART, ARINC-429, LIN, I2C, SPI, SENT, MIL-STD-1553, I2S, and related timing/trigger mechanisms.
• Designed, enhanced, and validated protocol totalizers and counters (Frames, Errors, Overflow, Reset, TX/RX) for CAN, UART, and ARINC429, including simulation and corner-case handling.
• Debugged complex protocol decoding discrepancies and error conditions, such as: CAN error frames, stuff errors, partial frames, SENT fast/slow CRC decode issues I2C repeated start and error row mismatches. Cross-platform decode inconsistencies across oscilloscope variants
• Performed extensive RTL simulation and verification using Cadence SimVision, validating protocol timing, error handling, and decode accuracy.
• Led timing analysis and optimization for FPGA designs using: Pipelining techniques, Chip Planner schematic analysis, Node-to-node critical path investigation for timing closure
• Used SignalTap logic analyzer extensively for real-time FPGA debug and validation on live oscilloscope hardware; correlated internal FPGA signals with waveform-level behavior using MobaXterm.
• Worked on timing-sensitive FPGA datapath logic for real-time protocol decode and trigger systems, focusing on deterministic behavior and low-latency processing pipelines.
• Applied pipelining and critical-path optimization techniques to improve timing performance and reduce RTL latency bottlenecks in protocol processing paths.
• Performed protocol parsing and streaming data analysis for high-speed serial communication interfaces, optimizing RTL pipelines for timing closure and stable hardware execution.

RTL Design Engineer at Optimized Solutions Limited (2023-06 – 2024-09)

RTL/HDL Engineer involved in architecture definition, RTL development, board bring-up, and validation for FPGA- and SoC-based systems. Worked on high-speed data acquisition, memory interfaces, communication protocols, and control algorithms, supporting both FPGA fabric and processor (HPS) domains.

• Defined FPGA architecture and modular design using VHDL/HDL, translating system-level requirements into implementable hardware blocks.
• Developed, simulated, and verified VHDL/HDL modules, followed by on-board testing and debugging on Xilinx and Intel FPGA platforms.
• Handled board bring-up and validation, including power-up checks, clocking, reset sequencing, and peripheral initialization using datasheets and reference designs.
• Interfaced and validated high-speed ADC and DAC devices: DAC2932, ADC LTC2314-14, AD9653
• Performed debugging and validation using DC590 evaluation board.
• Worked on Xilinx UltraScale Zynq and Intel Agilex / SoC platforms, including DE10-Nano, covering: SPI Flash, RS-232 UART, SPI, DDR4 (HPS side), Ethernet (1G & 10G), JTAG programming and debug
• Designed independent modular IP blocks in VHDL for: ADC interfaces, DAC interfaces, Control logic, using SPI and I2C protocols.
• Participated in root cause analysis (RCA) of FPGA issues during synthesis, implementation, and hardware execution using vendor toolchains.
• Supported customer requirement analysis as per tender specifications and contributed to technical documentation aligned with quality processes.

B.Tech in Electronics & Communication Engineering – University Institute of Engineering & Technology (UIET), MDU (2018-08 – 2022-09)

12th Grade in Non-Medical – D.A.V Public School, Sec 14, Gurgaon (2017-08 – 2018)

10th Grade – D.A.V Public School, Sec 14, Gurgaon (2015-08 – 2016)