Ec058 Ramya V

Entry-level ASIC Physical Design Engineer trained in RTL-to-GDSII flow with hands-on experience in floorplanning, placement, CTS, routing, and timing closure using Cadence Innovus, Tempus, and QRC across 28nm and 40nm technology nodes. Seeking an opportunity to contribute to backend VLSI/ASIC design teams.

Trainee – Physical Design Engineer - Moschip Academy of Silicon Systems & Technologies (MAST)

(2025-02)

• Executed complete RTL-to-GDSII flow at block level using Cadence Innovus
• Performed Pre-PnR checks, floorplanning, power planning, and placement optimization
• Built and optimized Clock Tree Synthesis (CTS) meeting skew and latency targets
• Achieved timing closure using Cadence Tempus with multi-Vt libraries
• Performed SI-aware routing, crosstalk analysis, and sign-off RC extraction using QRC
• Analyzed and resolved IR drop, DRC, and timing violations
• Gained understanding of correlation between PnR extraction and sign-off extraction

B.Tech - Electronics & Communication Engineering - Prathyusha Engineering College (2025-04)

Andhra Pradesh Board of Intermediate - BIIT Junior College (2021-04)

Andhra Pradesh Board of SSC - Oxford High School (2019-03)