Physical Design Engineer
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A technologist and an enthusiast with a vigor to explore new opportunities, learn new things and have a positive impact
Experienced Physical Design Engineer with over 8 years of expertise in semiconductor design and implementation, specializing in RTL-to-GDSII execution, floorplanning, and SOC integration. Proven track record in delivering high-performance PCIe, Display, and DTS IPs for advanced nodes (22nm, 14nm, 10nm, 7nm, and 5nm). Skilled in low-power design methodologies, EM/IR analysis, and physical verification(DRC/LVS/Density) processes.
Known for innovation, precision, and effective cross-functional collaboration in dynamic engineering environments.
Lead RTL-to-GDSII implementation for 10nm, 7nm, and 5nm technology nodes. Managed logic synthesis, floorplanning, placement, routing, and full sign-off processes. Executed low-power design closure, EM/IR analysis, and physical verification (DRC, LVS, Density, Antenna). Collaborated with global cross-functional teams to ensure efficiency and design robustness.
