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G. Sandhya 443

G. Sandhya 443

Post Silicon Validation Engineer

Talent
HyderabadMember since June 29, 2026
Post-Silicon ValidationGraphics validationBIOS flashingOS bring-upHDMIDisplayPortHDRHDCPVRRPSRDRRSDaisy-chain/MSTTDR logsETL tracesSOCwatchFRAPSCAPXFramesSystemVerilogUVMFunctional coverageAssertions3DMarkUnigine HeavenPCMarkHEVC Codec toolsDDUOpenGLOpenCLVulkanD3DX
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Post-Silicon ValidationGraphics validationBIOS flashingOS bring-upHDMI

About

Design Verification Engineer with 2 years of Post-Silicon Validation experience on Intel platforms and hands-on proficiency in SystemVerilog and UVM based verification. Skilled in debug, functional coverage, assertions, and building self-checking verification environments. Focused on delivering high-reliability SoC designs through coverage-driven verification methodology

Experience

Post-Silicon Validation Engineer - Wipro Ltd - Bangalore

(2022-05 - 2025-12)

Client: Intel. Graphics, Display & SoC Validation

  • Performed end-to-end validation on Intel platforms (Raptor Lake, Alder Lake) covering graphics driver stability, display protocol behavior, and multimedia subsystem features.
  • Validated HDMI, DisplayPort, HDR, HDCP, VRR, PSR, DRRS, and Dolby Vision across multiple OEM systems including Lenovo and Microsoft devices.
  • Executed gaming and performance workloads on Steam, Origin, Blizzard, Epic Games, and Microsoft Store using industry-standard benchmarks and graphics measurement tools for SoC integration testing.
  • Performed detailed silicon-level debug using HSD, TDR logs, ETL traces, and WPT, isolating and resolving 40+ hardware, firmware, and driver-level issues.
  • Reduced debug turnaround time by 15% by enhancing automation, log processing, and triage flow efficiency.
  • Collaborated with pre-silicon DV teams to align test plans, functional coverage goals, and failure traceability.
  • Executed validation for graphics driver releases, BIOS flashing, OS bring-up, and platform initialization across multiple Intel development systems.
  • Validated display and graphics functionality in HG/headless modes, indirect display, daisy-chain/MST configurations, and evaluated container/VM impact on GPU behavior (GPU Validation).
  • Experienced in verifying power management features, thermal interactions, and system-level performance dependencies.
  • Developed and executed test plans, regression suites, functional tests, smoke/sanity tests, and integration test scenarios.
  • Worked extensively with 3D APIs including OpenGL (OGL), OpenCL (OCL), Vulkan, and D3DX for graphics feature validation.
  • Utilized industry-grade tools such as 3DMark, Unigine Heaven, PCMark, HEVC Codec tools, SOCwatch, OPM, FRAPS, CAPXFrames, and DDU for performance and stability evaluation.
  • Improved regression cycle stability by 20% by refining triage workflows.
  • Reduced driver validation cycle time by 12% through workflow optimization.

Education

B.Tech - Electronics and Communication Engineering - PVPSIT (2018 - 2022)

Skills

Post Silicon Validation Engineer

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