Post Silicon Validation Engineer
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Design Verification Engineer with 2 years of Post-Silicon Validation experience on Intel platforms and hands-on proficiency in SystemVerilog and UVM based verification. Skilled in debug, functional coverage, assertions, and building self-checking verification environments. Focused on delivering high-reliability SoC designs through coverage-driven verification methodology
Post-Silicon Validation Engineer - Wipro Ltd - Bangalore
(2022-05 - 2025-12)
Client: Intel. Graphics, Display & SoC Validation
B.Tech - Electronics and Communication Engineering - PVPSIT (2018 - 2022)
