Hari Krishna Bandaru

FPGA/RTL Design Engineer with 2 years of hands‑on experience in hardware-software co-design, designing high-speed data paths, AXI based architectures, and real-time ADC and image processing pipelines on FPGA systems like Kria KV260 (ZCU102), ZCU104, and Spartan‑6 series. Skilled in RTL design (Verilog), clock-domain crossing (CDC) handling, High-Level Synthesis (Vitis HLS), PL-PS codesign, hardware bring-up, timing closure and on-chip debugging using ILA IP. Proven ability to deliver end‑to‑end FPGA solutions from architecture and RTL coding to hardware validation and system integration.

Design Engineer at Panacea Medical Technologies Pvt. Limited (2024-08 – Present)

• Designed RTL for a 256‑channel current‑to‑digital conversion ADC acquisition(17KSPS) system on Kria KV260 (ZCU102), handling clock-domain crossing (CDC) between ADC sampling and AXI‑Stream domains, and developed PS firmware (ARM Cortex‑A53) enabling high throughput real-time data capture and ethernet streaming.
• Designed RTL for a Dual‑channel current‑to‑digital conversion ADC acquisition(2KSPS) system on Micro-Chip SOC (M2S010-144TQ), developed PS firmware (ARM Cortex‑M3) and implemented Ethernet communication to backend (C#) systems.
• Designed RTL code to control Full Stepper motors to cover X, Y, Z positions at different speeds precisely, logging each motor's position.
• Designed MIPI CSI-2 capture and FPGA image-processing pipeline for SONY IMX415 sensor on ZCU104, developing key IP blocks using Vitis HLS (C++, pragma-based pipelining), including an HLS Remap IP to correct lens barrel distortion, for real-time object centroid detection.
• Displayed processed output images on a 4K monitor via DisplayPort for real-time visualization.
• Enhanced RTL for generator‑detector synchronization on Spartan‑6, integrating limit‑sensor feedback and timing‑based control logic.
• Implemented DDR based buffering to support high-bandwidth storage and continuous streaming of ADC and 4K image data.
• Established Wi-Fi communication to transfer Dual-Channel ADC data from master to slave.
• Proficient in debugging on-chip signals with ILA IP to improve signal visibility and resolve timing and signal issues.
• Performed hardware bring‑up, timing closure checks, simulation, and system‑level validation on target FPGA boards.
• Multi-Rate DSP System: Configured Xilinx FIR Compiler IP over AXI4-Stream for decimation-by-3 (120MHz to 40MHz) and interpolation-by-12 (40MHz to 480MHz) stages emulating a satellite downlink/uplink signal chain; developed a custom AXI4-Stream RTL module to capture and log the decimator output before feeding it into the interpolation stage, and verified behavior using MATLAB-generated input samples and FFT-based spectral analysis.

Advanced VLSI Design and Verification in VLSI Design and Verification – Maven Silicon (2023-01 – 2024-12)

Bachelor of Technologies in Electronics & Communication Engineering – St. Ann's College of Engineering & Technology (2020-01 – 2023-12)

Diploma in Electronics & Communication Engineering – Bapatla Engineering College (2017-01 – 2020-12)