Hemanth Babu S

Aspiring VLSI Design Engineer with hands-on experience in RTL design using Verilog and FPGA development. Strong foundation in digital design concepts and simulation, seeking an opportunity to contribute to ASIC/FPGA design in a semiconductor organization.

FPGA Design Intern – High-Speed Interface Protocols (USB 2.0/3.0) at VINCHIP SYSTEMS (2026-01 – 2026-05)

• Gained hands-on exposure to high-speed communication protocols, including USB 2.0 and USB 3.0 architecture and data transfer mechanisms.
• Studied USB protocol layers, packet structures, transfer types (Control, Bulk, Interrupt, and Isochronous), and link initialization procedures.
• Worked with Intel Cyclone III and Cyclone 10 FPGA development boards for protocol understanding, simulation, and hardware implementation activities.
• Acquired knowledge of ARM processor architecture and CPU organization concepts.
• Studied the RISC-V processor architecture and understood the functionality of major blocks including Program Counter (PC), Instruction Memory, Register File, ALU, Control Unit, Immediate Generator, and Data Memory.
• Understood instruction execution flow and data path operations for RISC-V and ARM-based processors.

Bachelor of Engineering in Electronics and Communication – K. RAMAKRISHNAN COLLEGE OF ENGINEERING (2021-08 – 2025-05)

Higher Secondary School – ST JOSESH'S COLLEGE OF HIGHER SECONDARY SCHOOL (2020-05 – 2021-06)

Secondary School – ST JOSESH'S COLLEGE OF HIGHER SECONDARY SCHOOL (2018-05 – 2019-06)