Hemanthakumar Hanumandhan

Simulated a quadratic-boost DC-DC converter achieving 34.4 times voltage gain during a research internship on renewable energy integration at NIT Calicut, hands-on with MATLAB/Simulink and LTspice.

Intern – MATLAB/Simulink (Phased-Array SATCOM Systems) at TRYNEUTERA ELECTRONICS PVT. LTD. (2026-09 – Present)

• Designed and simulated a 512-element (16 × 32) planar SATCOM phased-array antenna in MATLAB, implementing 6-bit per-element phase quantization for electronic beam steering.
• Authored a technical report on phased-array antennas covering working principles, analog/digital/hybrid beamforming and FPGA selection, recommending the AMD Zynq UltraScale+ RFSoC Gen 3 (XCZU48DR).
• Proposed an RFSoC-based hardware prototype with a 10-antenna (5 Tx / 5 Rx) configuration and presented the design to the engineering team.
• Developed a 200-element (20 × 10) 12.5 GHz miniature beam-steering array prototype using a Raspberry Pi Pico (RP2040) controller for phase look-up tables and SPI control of the beamformer IC.
• Executed a 32-element Ka-band metasurface prototype with complete MATLAB simulation; shift-register control (PIN diodes/varactors), validated by synthetic DSP (GNU Radio, NumPy) and SDR loopback.

Research Internship on Renewable Energy Integration by Power Converters at NATIONAL INSTITUTE OF TECHNOLOGY, CALICUT (2026-05 – 2026-07)

• Analyzed an enhanced-gain quadratic-boost DC-DC converter integrating a Quasi-Z-Source network and voltage-lift capacitors for renewable energy integration, under Dr. Raghuram M, Dept. of Electrical Engineering.
• Derived steady-state expressions for voltage gain, capacitor voltages, inductor current ripple, and device voltage stress, and validated each against simulation results.
• Performed simulations for the converter using LTspice and MATLAB/Simulink, attaining 34.4 times voltage amplification (10V to 344V) with 70% duty cycle — around 10 times higher than the conventional boost converter at the same duty cycle.
• Designed inductor and capacitor values from current- and voltage-ripple constraints, keeping device voltage stress below 90% of output voltage.
• Authored a complete technical report covering topology analysis, component design, and simulation validation.

Global Immersion Program – Mandarin Chinese at CHANG JUNG CHRISTIAN UNIVERSITY (2025-12 – 2025-12)

• Completed an intensive Mandarin Chinese program at Chang Jung Christian University, Taiwan, with students from multiple countries.
• Attended an industrial visit to Foxconn (Hon Hai precision industry) to gain exposure to global electronics manufacturing and technology industry practices.

Intern – In-Process Quality, Maintenance & Manufacturing at FORVIA FAURECIA (2025-06 – 2025-06)

• Provided assistance in optimizing the process and controlling quality during production, resulting in automation improvement leading to 15% reduction in manual inspection processes.
• Provided quality data collection and documentation procedures resulting in accurate process engineering team performance reports.
• Supported root-cause analysis of quality deviations, improving defect detection during production.

B. Tech in Electrical & Computer Engineering – Shiv Nadar University (Institution of Eminence), Delhi NCR (2028)