B.Tech Electronics & Telecommunication Engineering graduate (2026) seeking entry-level RTL/FPGA Design & Verification role
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B.Tech graduate in Electronics & Telecommunication Engineering (2026) seeking an entry-level RTL / FPGA Design & Verification role. Hands-on experience in RTL design (Verilog HDL, SystemVerilog), testbench development, and functional verification using ModelSim/QuestaSim, with working knowledge of UVM-based verification methodologies. Comfortable with the complete FPGA design flow (synthesis, simulation, functional verification) and eager to build hands-on proficiency with FPGA development tools such as Quartus, Vivado and Xilinx ISE while contributing to RTL programming, IP block development, and FPGA-based product development activities.
B.Tech - Electronics and Telecommunication Engineering - Dr. Babasaheb Technological University | D. N. Patel College of Engineering, Shahada (2022-06 - 2026-07)
12th (HSC) - D. R. Junior College, Nandurbar (2022-06)
10th (SSC) - Abhinav Vidhyalay, Nandurbar (2020-06)
