RTL Design Engineer (Intern) at Cadence Design Systems (2025-07 – Present)
RTL design and verification of CXL protocol implementation
- Debugged RTL design of the Application layer for the industry-standard CXL protocol by enabling 40+ test cases to be passed, exceeding defined verification criteria within the IP Design team.
- Designed and integrated a Memory-Mapped I/O AXI (AMBA AXI) interface between the CXL register block RTL and CXL application layer RTL, meeting verification criteria defined in block requirement specifications.
- Leveraged AI tools to automate repetitive tasks and enhance design efficiency.
FPGA Design Engineer (Intern) at Astrogate Labs (2025-01 – 2025-06)
Satellite-ground laser alignment system for ISRO payload
- Developed a satellite-ground laser alignment system for an ISRO payload; developed an RTL-based weighted centroid algorithm to track beacon laser spots on photodetectors with high precision.
- Performed hardware bring-up and board-level debugging of the solution on a ZYBO Z7 FPGA development board, achieving 95% accuracy in real-time centroid calculations.
- Validated signal output and timing behavior using lab instrumentation including oscilloscopes and logic analysers during bring-up phases.
FPGA Design Engineer (Intern) at CSIR-CSIO (2024-05 – 2024-07)
Defence-grade Landmine Detection via Autonomous Drone project
- Contributed to a defence-grade Landmine Detection via Autonomous Drone project; developed and optimised a high-performance video processing system using ARINC 818-2 protocol IP.
- Implemented the system on a PYNQ-Z1 FPGA platform using Xilinx Vivado Design Suite; performed functional verification through real-time HDMI display connection.
