Jatin Savle

HMI Control Logic and Context-Aware Interface Design with Multi-Protocol Telemetry Architecture (GSM, RS485, Ethernet) for High-Power Industrial Cathodic Protection Pipeline Rectifier Unit in Oil & Gas Industries.

Modular

Hardware/Firmware Architectures enabling Optional Integration of Reference Protection, Timer Interruption, Data Logging, GSM/Ethernet Telemetry and Temperature Controls beyond standard CC/CV modes.

Standalone

Solar-Powered CP Module integrating an MPPT Battery Charge Controller with a Dedicated Output DC/DC Converter driven by Op-Amp-based PID Control for Auto/Manual Transitions and CC/CV Regulation.

Design Engineer at Kristron Controls & Systems Pvt. Ltd. (2025-05 – 2026-08)

• HMI Control Logic and Context-Aware Interface Design with Multi-Protocol Telemetry Architecture (GSM, RS485, Ethernet) for High-Power Industrial Cathodic Protection Pipeline Rectifier Unit in Oil & Gas Industries.
• Modular Hardware/Firmware Architectures enabling Optional Integration of Reference Protection, Timer Interruption, Data Logging, GSM/Ethernet Telemetry and Temperature Controls beyond standard CC/CV modes.
• Standalone Solar-Powered CP Module integrating an MPPT Battery Charge Controller with a Dedicated Output DC/DC Converter driven by Op-Amp-based PID Control for Auto/Manual Transitions and CC/CV Regulation.
• High-Power Synchronous Buck Converter integrating External MOSFET Power Stage, Precision Shunt-Based Current Sensing, Dual Constant-Voltage/Constant-Current Control Loops and Rigorous Thermal Management.
• PWM Generation and Control Board for a DC Backup Stage of Dual-Input CP Rectifier Unit with Optocoupler-Isolated Duty-Cycle Regulation, AC-Shutdown Interlocks and IGBT Desaturation/Short-Circuit Protection.
• Bidirectional Cellular GSM-to-Modbus Protocol Conversion Gateway with Parameter-Name Payload Parsing, Asynchronous Serial Ring-Buffer Queues, Non-Blocking State Machines, and Hardware Timing Interlocks.

Summer Intern at Reliance Jio Infocomm Ltd. (2018-05 – 2018-10)

• Worked in PAN India IP/MPLS domain while being part of NOC/Core Hardware TAC involving TNAs, L4, L3 and L2 Engineers along with Documenting HLD-LTE Core Network Architectures' Qualitative Analysis for Jio.

M.Tech in Electricals [Power Electronics & Power Systems] – IIT Bombay (2021 – 2024)

B.Tech in Electronics [Power Electronics & VLSI Systems] – IIITDM Kancheepuram (2014 – 2019)