Kalyan Kumar

ASIC Physical Design intern with hands-on RTL-to-GDSII flow experience across floorplanning, placement, CTS, routing, and timing closure. Skilled in Verilog, logic synthesis, STA, physical verification, and TCL/Python scripting, with exposure to Synopsys Design Compiler and PrimeTime, and working knowledge of DFT and signal integrity concepts using OpenLane and SKY130 PDK.

Project Intern - IIIT Hyderabad

(2025-05 - 2025-07)

• Developed intelligent programs using natural language toolkits and structured data sources to generate content.
• Contributed to feature development and fixes based on the Wikipedia Community Wishlist.

RTL to GDSII Intern - NIELIT, Noida

(2025-06 - 2025-08)

• Gained hands-on experience in the complete ASIC design flow including RTL design using Verilog, Logic Synthesis, STA, Floorplanning, Placement, Clock Tree Synthesis (CTS) optimization, Routing, Parasitic Extraction, Timing Closure, DRC, and LVS.
• Applied TCL scripting to automate verification processes and ensure compliance with foundry-specific design rules.

B.Tech - Electronic Communication Engineering - G Pulla Reddy Engineering College, Andhra Pradesh (2021 - 2025)