Karan Maniyar
Electronics & Telecommunication Engineering
Talent
MumbaiMember since October 1, 2026
SystemVerilogVerilogAssertionsSPIUARTXilinx VivadoXilinx ISEMimas V2 (Spartan-6)Digital Logic Design
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SystemVerilogVerilogAssertionsSPIUART
About
Worked with the Analog Mixed-Signal (AMS) Verification team at Cyient – first industry exposure to semiconductor verification flows. Practiced writing SystemVerilog testbenches and assertions across communication protocols (UART, SPI, AXI), and implemented Verilog-A, wreal, and real-number models for basic analog blocks such as a comparator – building hands-on understanding of how AMS verification engineers approach mixed-signal blocks.
Experience
AMS Verification Intern at Cyient (2026-06 – 2026-07)
- Worked with the Analog Mixed-Signal (AMS) Verification team at Cyient – first industry exposure to semiconductor verification flows.
- Practiced writing SystemVerilog testbenches and assertions across communication protocols (UART, SPI, AXI), and implemented Verilog-A, wreal, and real-number models for basic analog blocks such as a comparator – building hands-on understanding of how AMS verification engineers approach mixed-signal blocks.
Education
Bachelor of Technology in Electronics & Telecommunication Engineering – Thadomal Shahani Engineering College, Mumbai (2023 – 2027)
Skills
Electronics & Telecommunication Engineering
