Analog Design & Verification Intern - MMRFIC Technologies Pvt. Ltd - Bengaluru
(2024-02 - 2024-06)
- Learned Analog IC design flow using Cadence Virtuoso
- Designed and simulated CMOS Inverter, Logic Gates, Transmission Gate, and D Flip-Flop
- Performed DC, AC, and Transient analysis
- Worked on the verification of a 10-bit SAR ADC (90 nm)
- Verified Bootstrap Switch, Comparator, CDAC, and SAR ADC functionality
- Verified analog and digital outputs across PVT conditions
Analog Verification Engineer - MMRFIC Technologies Pvt. Ltd - Bengaluru
(2024-07 - 2025-05)
- Verified PLL, including Band gap Reference (BGR) and VCO performance
- Performed analog verification of AUX ADC WLAN TX, WLAN RX, SPO2 RX
- Verified gain, bandwidth, stability, calibration, functionality, and performance across PVT conditions using Cadence Virtuoso
Post-Silicon Validation Engineer - MMRFIC Technologies Pvt. Ltd - Bengaluru
(2025-06 - 2026-03)
- Performed silicon bring-up and validation of the PLL
- Performed post-silicon validation of AUXADC, WLAN TX, WLAN RX, SPO2 RX, SPO2 TX
- Conducted hardware testing using Oscilloscope, Spectrum Analyzer, Signal Generator, Digital Multimeter, and DC Power Supply
- Compared silicon results with Cadence simulation results and documented silicon issues
Analog Design & Silicon Debugging Engineer - MMRFIC Technologies Pvt. Ltd - Bengaluru
(2026-03)
- Improved the SPO2 RX Switch Matrix by reducing switch ON resistance
- Increased supported photodiode current from approximately 10 UA to 150 UA
- Improved gain linearity and reduced saturation
- Investigated silicon issues identified during validation
- Performed root cause analysis and implemented design fixes
- Improved WLAN RX gain performance from 52 dB to 60 dB in 2 MHz mode
- Verified design improvements through simulation and post-silicon validation
