Graduate student pursuing M.Tech in VLSI Design
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Graduate student pursuing an M.Tech in VLSI Design, seeking an internship in Digital VLSI, RTL Design, and Physical Design. Skilled in RTL coding with Verilog, digital circuit fundamentals, and hands-on exposure to Cadence Virtuoso and Genus for analog/CMOS layout and verification. Familiar with basic C-Shell scripting. Eager to contribute to RTL design, DFT insertion, physical design, and physical verification tasks within an ASIC/SoC design environment.
M.Tech - VLSI Design - Vellore Institute of Technology, Amaravati (2025-01 - 2027-12)
B.Tech - Electronics and Communication Engineering - St. Mary's Group of Institutions, Hyderabad (2019-01 - 2023-12)
Intermediate - MPC - Resonance Junior College, Khammam (2017-01 - 2019-12)
